Analysis of Sram Reliability under Combined Effect of Transistor Aging, Process and Temperature Variations in Nano-scale Cmos

As dimensions of MOS devices have been scaled down, new reliability problems are coming into effect. One of these emerging reliability issues is aging effects which result in device performance degradation over time. NBTI (Negative biased temperature instability) and PBTI (Positive biased temperature instability) are well known aging phenomenon which are limiting factors for future scaling of devices. NBTI results in Vt (threshold voltage) degradation of PMOS and PBTI results Vt degradation in the NMOS due to the generation of trapped charges. In nano-scale CMOS technologies, process (threshold voltage) and temperature variations are also crucial reliability concerns. On the other hand, NBTI and PBTI are also dependent on temperature and threshold voltage. In this project, the combined effect of transistor aging, process and temperature variations on the reliability of the 6T SRAM (Static Random Access Memory) in 32nm CMOS technology is analyzed in terms its performance metrics: SNM (Static Noise Margin), Write Margin, Access time and leakage. We analyzed that performance of SRAM degrades over time under aging effect. It is observed that low Vt SRAM at high temperature suffers most performance degradation. Due to the degradation of SRAM performance, number of faulty cells rises over time. We also observed the effect of supply voltage variation of the SRAM. We observed that performance degradation is minimal at nominal supply voltage. Our results show that adaptive supply voltage can be used to save power over time in active mode. I certify that the Abstract is a correct representation of the content of this thesis. _________________________ ____________ Chair, Thesis Committee Date ACKNOWLEDGEMENTS I would like to thanks my thesis advisor Dr. Hamid Mahmoodi for his invaluable guidance and support towards the completion of my thesis. I would also like to thanks to my committee member Dr. Hao Jiang for his timely support and feedbacks. I am also thankful to the school of engineering for me the resources required for completing my project. Finally, I would like to thank the whole team of NeCRC (Nano-electronics Computing and Research Center), my family and friends for their support. Abstract Acknowledgments 1. Introduction